The present invention relates to magnetic recording and, particularly, to an improved synchronization detector.
Sampled amplitude detectors used in magnetic recording require timing recovery in order to correctly extract the digital sequence. As shown in FIG. 1, data sectors 100 on magnetic disks are formatted to include an acquisition preamble 102, a sync or synchronization mark 104, and user data 106. Timing recovery uses the acquisition preamble 102 to acquire the correct sampling frequency and phase before reading the user data 106. The synchronization mark 104 demarcates the beginning of the user data.
The preamble 102 is written using the periodic non-return-to-zero (NRZ) sequence 001100110011 . . . which causes the pattern of magnetization SSNNSSNNSSNN . . . to be written on the magnetic medium. The pattern is periodic, having period 4T, where T is the bit period. The pattern is sometimes called a 2T pattern because the interval between successive magnetic field direction transitions is 2T. During the read operation, the sequence of samples [xi, xi+1, . . . ], produced by the preamble is also of period 4T. In the case of PR4 (partial response) equalization, the sequence is ideally [1,1,xe2x88x921,xe2x88x921,1,1,xe2x88x921,xe2x88x921,1,1, . . . ,]. In the case of EPR4 (extended partial response) equalization, it is [2,0,xe2x88x922,0,2,0,xe2x88x922,0,2,0, . . . ]. In the general case of EnPR4, it is the convolution [1,1]n *[1,1,xe2x88x921,xe2x88x921,1,1,xe2x88x921,xe2x88x921,1,1, . . . ].
The preamble 102, the sync mark 104, and the user data 106 are read in succession. Reading the preamble 102 establishes bit synchronization. Reading the sync mark 104 establishes the absolute bit index of the first bit of the user data 106. Once bit synchronization is established, the sync mark 104 is searched for beginning at each possible bit index (i.e., at each possible start value in the sequence) within a predetermined qualification window, the onset and time-out of which are a priori parameters. Typically, this search is done by calculating a distance metric between the ideal sequence of signal samples [s0, s1, . . . , sLxe2x88x921] expected at the synchronization mark 104 and each block of received samples [xi, xi+1, . . . , xi+Lxe2x88x921], where the index i runs through all the bit indices in the qualification window. Typically, the first index i for which the metric does not exceed a qualification threshold is asserted to be the location of the synchronization mark 104.
The prior art suffers from disadvantages in that a period T clock is required to clock the synchronization detector. In addition, a relatively long synchronization mark is required.
These and other drawbacks in the prior art are overcome in large part by a system and method according to the present invention. According to one implementation, a synchronization detector uses the periodicity of the preamble to limit the search for the synchronization mark. In one implementation, the search is limited to one bit phase in each block of four (4) bits. In another implementation, the search is limited to one bit phase per block of two (2) bits.
Briefly, the synchronization mark is written beginning at a known, fixed phase of the periodic preamble pattern. The signal phase estimate obtained in the course of reading the preamble is used to limit the search for the synchronization marks to the bit positions whose phase matches the estimate of the fixed, known phase.
A synchronization detector according to an embodiment of the invention includes a phase detector and a distance metric calculator. The phase detector uses the preamble readback signal to estimate the bit periods and outputs a signal indicative of this estimate. This signal is used by the distance metric calculator to limit its search for the synchronization mark to every mth bit position, where m is a predetermined integer greater than one (1).
Advantageously, the present invention allows the synchronization detector to operate on a period mT clock. Thus, the synchronization detector may use a lower speed, less expensive clock. In addition, the synchronization detector may be relatively shorter than required when m=1 to achieve a given probability of correct synchronization in the presence of noise.